Title:
リードカット装置および半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4921016
Kind Code:
B2
Abstract:
Aimed at stably forming sheared surfaces of leads of semiconductor devices, and at raising ratio of formation of plated layers onto the sheared surfaces of the leads, a lead cutter has a die 106, and a cutting punch 110 having a cutting edge at least on the surface facing the die, wherein clearance T between the die 106 and the cutting punch 110 is set within the range from not smaller than 2.3% and smaller than 14.0% of the total thickness of the leads to be cut and plated layers formed on the upper and the lower surfaces thereof.
Inventors:
Kumamoto Tohru
Application Number:
JP2006097608A
Publication Date:
April 18, 2012
Filing Date:
March 31, 2006
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L23/50; B21D28/16; B23D15/08
Domestic Patent References:
| JP2003124417A | ||||
| JP2004354374A | ||||
| JP2004127984A | ||||
| JP3283556A | ||||
| JP11254054A | ||||
| JP8023060A | ||||
| JP7211838A | ||||
| JP6069394A | ||||
| JP9276952A | ||||
| JP3227044A | ||||
| JP8057557A | ||||
| JP11031774A | ||||
| JP2005113180A |
Attorney, Agent or Firm:
Shinji Hayami