Title:
マイクロ構造体の製造方法
Document Type and Number:
Japanese Patent JP4102158
Kind Code:
B2
Abstract:
A method is for manufacturing a microstructure having a thin-walled portion with use of a material substrate. The material substrate has a laminated structure which includes a first conductor layer 101 , a second conductor layer 102 , a third conductor layer 103 , a first insulating layer 104 interposed between the first conductor layer and the second conductor layer, and a second insulating layer 105 interposed between the second conductor layer and the third conductor layer. The first insulating layer is patterned to have a first masking part for covering a thin-wall forming region of the second conductor layer. The second insulating layer is patterned to have a second masking part for covering the thin-wall forming region of the second conductor layer. The method includes forming the thin-walled portion in the second conductor portion by etching the material substrate from the first conductor layer down to the second insulating layer via a mask pattern 58 including a non-masking region corresponding to the thin-wall forming region of the second conductor layer.
Inventors:
Takama Satoru
Yoshihiro Mizuno
Osamu Tsuboi
Okuda Hisao
Hiromitsu Soneda
Ueda Tomofumi
Ippei Sawaki
Yoshitaka Nakamura
Yoshihiro Mizuno
Osamu Tsuboi
Okuda Hisao
Hiromitsu Soneda
Ueda Tomofumi
Ippei Sawaki
Yoshitaka Nakamura
Application Number:
JP2002310314A
Publication Date:
June 18, 2008
Filing Date:
October 24, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G02B26/08; B81C1/00; H01L29/84
Domestic Patent References:
| JP11211483A | ||||
| JP2002301698A | ||||
| JP798409A |
Attorney, Agent or Firm:
Minoru Yoshida
Tatsuya Tanaka
Yoshikazu Fukumoto
Tatsuya Tanaka
Yoshikazu Fukumoto
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