Title:
MANUFACTURING METHOD OF MULTILAYER CIRCUIT BOARD
Document Type and Number:
Japanese Patent JP3855670
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer circuit board having highly accurate inner-via-hole connections.
SOLUTION: The manufacturing method includes a lamination process for sticking at least on one side of a core material 1 compressible insulating base materials 7, 8 having respectively mold releasing films 5, 6; a hole machining process for so forming via holes 9, 10 in the base materials 7, 8 as to make visible the surfaces of circuit patterns 2, 3 of the core material 1; a paste filling process for filling conductive pastes 11, 12 into the via holes 9, 10, and thereafter, peeling therefrom the mold releasing films 5, 6; a hardening process for so sticking respectively metal foils 13, 14 on the base materials 7, 8 as to connect electrically the metal foils 13, 14 with the circuit patterns 2, 3 of the core material 1 by the heating and pressing of the metal foils 13, 14; and a pattern forming process for so processing the metal foils 13, 14 as to form circuit patterns 15, 16. In the manufacturing method, the inner-via-hole connections of the conductive pastes 11, 12 with the circuit patterns 2, 3 of the core material 1 are made highly accurate.
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Inventors:
Akio Ochi
Shinji Hirata
Kenichiro Hori
Akira Wada
Shuji Ida
Shinji Hirata
Kenichiro Hori
Akira Wada
Shuji Ida
Application Number:
JP2001084786A
Publication Date:
December 13, 2006
Filing Date:
March 23, 2001
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H05K3/40; H05K3/46; H05K3/00; (IPC1-7): H05K3/46; H05K3/00; H05K3/40
Domestic Patent References:
| JP2000223809A | ||||
| JP1041628A | ||||
| JP1187870A |
Attorney, Agent or Firm:
Fumio Iwahashi
Hiroki Naito
Daisuke Nagano
Hiroki Naito
Daisuke Nagano