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Patent Searching and Data


Title:
MANUFACTURING METHOD OF MULTILAYER WIRING BOARD
Document Type and Number:
Japanese Patent JP2007208229
Kind Code:
A
Abstract:

To propose a manufacturing method permitting the efficient manufacture of a multilayer wiring board and an improvement in the reliability of interlayer conduction connection of a stacked via or the like.

In an insulating resin substrate 1, there is formed a via hole 2 having the maximum diameter that is twice or less the thickness of a wiring conductor to be formed. In the insulating resin substrate with the via hole formed, a base metal layer 3 and a resist film 4 are formed. An electrolytic plating metal 5 is deposited by electrolytic plating to form a wiring conductor of a predetermined thickness and fill the via hole conductor at the same time. By stacking a predetermined kind and number of single-layer wiring boards 6 obtained in this way to press them, a multilayer wiring board is formed.

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
MIYAZAKI MASASHI
YOKOTA HIDEKI
Application Number:
JP2006051137A
Publication Date:
August 16, 2007
Filing Date:
January 31, 2006
Export Citation:
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Assignee:
TAIYO YUDEN KK
International Classes:
H05K3/46
Domestic Patent References:
JP2004023002A2004-01-22
JPH09312472A1997-12-02
JP2002158447A2002-05-31
JP2004193370A2004-07-08
Foreign References:
WO2004103039A12004-11-25