Title:
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3420745
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To avoid separation of laminated plating layers, when performing wire bonding on an inner lead having a laminated plated structure.
SOLUTION: A semiconductor chip 3 is bonded to a die pad 2 of a lead frame 1, having laminated plated layers made of nickel, palladium, and gold. Then, a metallic thin wire 6, made of gold is pressed with a load of approximately 60 g against an electrode pad 4 of the semiconductor chip 3 via a bonding tool 20, and ultrasonic waves having an output of approximately 55 mW is applied to perform first bonding process. Next, the metallic thin wire 6 is pressed with a load of 150 to 250 g against an inner lead 5, and ultrasonic wave with an output of 0 to 20 mW is applied to perform the second bonding process. In a second bonding process, bonding appropriate to the characteristics of the laminated plating layers is performed with a large pressing load and a small output of ultrasonic waves. This enables strong bonding in a short time, without causing peeling of a gold plated layer.
Inventors:
Arakawa definition
Makoto Ito
Kenichi Nishiyama
Maruyama Koei
Makoto Ito
Kenichi Nishiyama
Maruyama Koei
Application Number:
JP2000318898A
Publication Date:
June 30, 2003
Filing Date:
June 24, 1997
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/60; H01L23/50; (IPC1-7): H01L21/60; H01L23/50
Domestic Patent References:
| JP2297949A | ||||
| JP6378560A | ||||
| JP9307054A | ||||
| JP4324947A | ||||
| JP4337657A | ||||
| JP4287356A | ||||
| JP521693A | ||||
| JP5326650A |
Attorney, Agent or Firm:
Hiroshi Maeda (7 outside)