Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4055334
Kind Code:
B2
Abstract:
The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.
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Inventors:
Naoki Komai
Takeshi Nogami
Kito Eiji
Taguchi Mitsuru
Takeshi Nogami
Kito Eiji
Taguchi Mitsuru
Application Number:
JP2000176216A
Publication Date:
March 05, 2008
Filing Date:
June 13, 2000
Export Citation:
Assignee:
ソニー株式会社
International Classes:
C25D5/48; H01L21/288; C25D7/12; H01L21/3205; H01L21/321; H01L21/3213; H01L21/768
Domestic Patent References:
| JP4507326A | ||||
| JP10321561A | ||||
| JP2001514332A |
Attorney, Agent or Firm:
Funabashi Kuninori