Title:
半導体装置の製造方法および半導体装置
Document Type and Number:
Japanese Patent JP5801221
Kind Code:
B2
Abstract:
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
Inventors:
Masayuki Kitamura
Atsuko Sakata
Makoto Wada
Yuichi Yamazaki
Masayuki Katagiri
Akihiro Kajita
Tadashi Sakai
Naoshi Sakuma
Ichiro Mizushima
Atsuko Sakata
Makoto Wada
Yuichi Yamazaki
Masayuki Katagiri
Akihiro Kajita
Tadashi Sakai
Naoshi Sakuma
Ichiro Mizushima
Application Number:
JP2012036377A
Publication Date:
October 28, 2015
Filing Date:
February 22, 2012
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/3205; C23C16/26; H01L21/28; H01L21/285; H01L21/768; H01L23/532
Domestic Patent References:
| JP2011023420A | ||||
| JP2009164432A | ||||
| JP2005332878A | ||||
| JP2000183064A | ||||
| JP9172077A | ||||
| JP4256313A | ||||
| JP7094515A | ||||
| JP2009070911A |
Foreign References:
| US20100021708 |
Attorney, Agent or Firm:
Suzue International Patent Office