Title:
配線基板の製造方法
Document Type and Number:
Japanese Patent JP7424741
Kind Code:
B2
Abstract:
To provide a method for manufacturing a wiring board including a fine wiring layer excellent in chip transfer with a good yield and at low costs.SOLUTION: A method for manufacturing a wiring board includes the steps of: forming an insulation material layer on a support substrate; forming a first opening in the insulation material layer; modifying a surface of the insulation material layer; forming a first seed layer on the modified surface of the insulation material layer by electroless nickel plating; forming a second seed layer on the first seed layer by electroless copper plating; forming a resist for wiring formation including an opening communicating with the first opening and a recess reaching the second seed layer on the second seed layer; filling the first opening, the opening, and the recess with a conductive material by electrolytic plating; peeling the resist; and removing the first and second seed layers in a region exposed by resist peeling.SELECTED DRAWING: Figure 3
Inventors:
Masaya Toba
Kazuhiko Kurabuchi
Takashi Masuko
Shinichiro Abe
Mitsukura and his group
Kazuhiko Kurabuchi
Takashi Masuko
Shinichiro Abe
Mitsukura and his group
Application Number:
JP2018104511A
Publication Date:
January 30, 2024
Filing Date:
May 31, 2018
Export Citation:
Assignee:
Resonac Co., Ltd.
International Classes:
H05K3/18; H05K3/38
Domestic Patent References:
| JP201010639A | ||||
| JP2003347724A | ||||
| JP201373994A | ||||
| JP201711010A | ||||
| JP2009290003A |
Foreign References:
| WO2010098235A1 |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshinori Shimizu
Hiroyuki Hirano
Youhei Suzuki
Yuji Wada
Yoshinori Shimizu
Hiroyuki Hirano
Youhei Suzuki
Yuji Wada