To measure an error in a pseudo random (PN) pattern whose mark rate is varied without increasing the circuit scale.

Outputs of a PN pattern generating circuit 1a and a PN pattern generating circuit 1b which provide an output of a serial PN pattern whose mark rate is 1/2 and whose bit phase relation is controlled by a phase control circuit 2 are ANDed by an AND circuit 3. A comparator circuit 5 compares the output from the AND circuit 3 with data to be measured bit by bit, provides an output of number of pulses by number of erroneous bits, and an error counter 6 counts number of the pulses outputted from the comparator circuit 5. A setting value to change optionally a phase relation between the output of the PN pattern generating circuit 1a and the output of the PN pattern generating circuit 1b is fed to the phase control circuit 2.