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Title:
MASK PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPH07182231
Kind Code:
A
Abstract:

PURPOSE: To reduce the hardware without increasing the load and processing time of a CPU by using only one mask circuit system.

CONSTITUTION: Data are stored in plural memories M1 to Mn without masking them. When one memory M is selected out of the plural memoris M1 to Mn by a bus interface 4, the CPU 1 rewrites the contents of a register R to masking data corresponding to the selected memory M and the masking data are supplied to a masking circuit S. The circuit S masks bits other than objective bits out of data stored in the selected memory M based upon the masking data and only specific bits to be processed are outputted to the CPU 1.


Inventors:
SAITO HISASHI
Application Number:
JP32659093A
Publication Date:
July 21, 1995
Filing Date:
December 24, 1993
Export Citation:
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Assignee:
ASIA ELECTRONICS
International Classes:
G06F12/06; (IPC1-7): G06F12/06
Attorney, Agent or Firm:
Toru Yui (2 outside)



 
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