PURPOSE: To obtain a low capacitance macro cell using a small number of basic elements and improve relative accuracy of macro cells in a master slice semiconductor integrated circuit having a capacitive element formed therein.

CONSTITUTION: A plurality of polysilicon regions 3 of the same shape are formed on a semiconductor region 4 with an insulating film in-between to form a basic capacitive element. A plurality of such basic elements are arranged. The position and number of wiring connecting holes 5, located in the polysilicon regions 3, are varied depending on a desired capacitance, and then wiring regions 6 are connected to the polysilicon regions 3. Thus each macro cell is provided with desired capacitance. The above-mentioned constitution needs only one basic element to obtain low capacitance, and improves relative accuracy of macro cells.