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Title:
MATCHED FILTER CIRCUIT
Document Type and Number:
Japanese Patent JP2000013188
Kind Code:
A
Abstract:

To suppress power consumption by sequentially holding digital voltage signal with registers, holding a plurality of coefficients of one bit, which correspond to the registers, in a shift register, calculating the exclusive OR of the digital voltage signals and the coefficients and converting the total sum of outputs into an analog current signal.

In the analog addition circuit ADD of a current type, the four-bit outputs of exclusive OR circuits XOR1-XORn are inputted to the gates of switches T11-T14,..., Tn1-Tn4. When outputs are in high levels, the switches are closed. Constant current sources I11-I14,..., In1-In4 connected to the drains of the respective switches supply the current of a current value corresponding to the weight of the bit connected to the switch. When the switch is closed, the currents are supplied to the source of the switch connected to a common output terminal and the total sum of the currents flowing in the respective switches is outputted as Aout.


Inventors:
SHU NAGAAKI
SHU TERUHEI
SUZUKI KUNIHIKO
Application Number:
JP19250198A
Publication Date:
January 14, 2000
Filing Date:
June 23, 1998
Export Citation:
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Assignee:
YOZAN INC
International Classes:
G06G7/14; G06G7/19; H03H17/02; H04B1/707; H04B1/7093; (IPC1-7): H03H17/02; G06G7/14; G06G7/19; H04B1/707
Attorney, Agent or Firm:
Yamamoto Makoto