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Patent Searching and Data


Title:
MAXIMUM CORRECTION LIMITING TYPE ECHO CANCELLER
Document Type and Number:
Japanese Patent JPS63279622
Kind Code:
A
Abstract:

PURPOSE: To increase the stability by adding a signal to an output of a delay storage circuit by an adder circuit after a maximum/minimum value of a coefficient calculated by a coefficient correction counter circuit with respect to the correction value so as to reduce the converging speed.

CONSTITUTION: A maximum/minimum value limit circuit 9 limits the maximum/ minimum value calculated by a coefficient correction calculation circuit 8. The adder circuit 10 adds the output of the maximum/minimum limit circuit 9 and the impulse response of the 2nd delay storage circuit 7 and outputs the added output to the 2nd delay storage circuit 7. Thus, the maximum correction of the impulse response is limited, and the converging speed is decreased thereby increasing the stability. Since a small correction is applied while the maximum value and the minimum value are limited, the adaptive operation of the echo canceller is kept constant.


Inventors:
MARUYAMA TADASUKE
Application Number:
JP11260787A
Publication Date:
November 16, 1988
Filing Date:
May 11, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04B3/23; (IPC1-7): H04B3/23
Attorney, Agent or Firm:
Masaki Yamakawa