Title:
MEMORY ACCESS CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP3691340
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a memory access control circuit capable of developing the performance of a controller to the maximum.
SOLUTION: An address signal, a CS signal, and a We signal whose active periods are different from each other are applied to a controller 22a of a memory card 22, and an ID data signal is read from a memory 22b. A CPU 12 checks the validity of each read ID data signal. Concretely, value of common data included in the ID data signal is compared with a prescribed value, and when the common data value indicates the prescribed value, it is judged that the ID data signal is proper, but when the common data value does not indicate the prescribed value, it is judged that the ID data signal is not proper. The CPU 12 decides the shortest active period among the active periods when the legal ID data signal is read as an optimal active period.
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Inventors:
Akira Toba
Application Number:
JP2000137508A
Publication Date:
September 07, 2005
Filing Date:
May 10, 2000
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
G06F12/00; G06F12/06; G06K17/00; H04N5/907; (IPC1-7): G06F12/00; G06F12/06; G06K17/00; H04N5/907
Domestic Patent References:
| JP2000232619A | ||||
| JP7110796A | ||||
| JP4155456A | ||||
| JP2001222462A | ||||
| JP2037590A | ||||
| JP62078640A | ||||
| JP5103291A | ||||
| JP2248169A | ||||
| JP2000013729A | ||||
| JP6350907A | ||||
| JP10233986A |
Attorney, Agent or Firm:
Yoshito Yamada
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