PURPOSE: To remove restrictions on access to bank memory areas in the read cycle and to access some bank memory area without hindrance in the write cycle by controlling the setting of validation/invalidation of the band area indication of an indicating means based on a discriminated bus cycle classification.

CONSTITUTION: An address decoder 11 performs the decoding processing of an address by an address signal and an MI/O signal for distinction between memory access and I/O access. A read/write cycle discriminating circuit 12 discriminates whether the pertinent bus cycle is a read cycle or a write cycle before a command is outputted. A control means (an AND gate 15, a NAND gate 16 of negative logic, and an inverter 17) controls setting of validation/ invalidation of the band area indication of a bank register 13 based on the bus cycle classification discriminated by the discriminating circuit 12. Thus, the memory and the bank to be accessed are switched between the read cycle and the write cycle without hindrance and are accessed.