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Patent Searching and Data


Title:
MEMORY BACKUP SYSTEM FOR CPU
Document Type and Number:
Japanese Patent JPH0546496
Kind Code:
A
Abstract:

PURPOSE: To prevent the recovery of processing based on unauthorized data and to improve reliability by checking a will written in a RAM at turning off the power source when the power supply is restarted.

CONSTITUTION: A CPU 25 is provided with an interrupt reset part 26 with an interrupt terminal XIRQ and a reset terminal RESET receiving a voltage deterioration signal, a data transfer part 28 transferring the information in the CPU25 to an external RAM 29, and a will write part 27 writing the prescribed will to the external RAM 29. In this case, the data transfer part 28 writes the information in the CPU25 on the external RAM 29 in response to the interrupt terminal XIRQ receiving a voltage deterioration signal, writes the prescribed will to the external RAM 29, starting the reset processing of the CPU 25. After that, when the power supply voltage rises, the perfection of the will stored in the external RAM 29 is confirmed and the information in the CPU 25 is accurately held in the external RAM 29. Thus, the reliability can be improved.


Inventors:
KIKUKAWA YOICHI
KOJIMA TAKEKATSU
MATSUMOTO TAKAAKI
Application Number:
JP22527891A
Publication Date:
February 26, 1993
Filing Date:
August 12, 1991
Export Citation:
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Assignee:
MOTOROLA JAPAN
International Classes:
G06F1/28; G06F1/30; G06F12/16; (IPC1-7): G06F1/28; G06F1/30; G06F12/16
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)