Title:
メモリセルの構造試験
Document Type and Number:
Japanese Patent JP2004530243
Kind Code:
A
Abstract:
An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.
Inventors:
Trip, michael
Mc, Taku
Spica, michael
Mc, Taku
Spica, michael
Application Number:
JP2002578510A
Publication Date:
September 30, 2004
Filing Date:
March 08, 2002
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G01R31/28; G11C11/401; G11C11/413; G11C29/02; G11C29/34; G11C29/50; (IPC1-7): G11C29/00; G01R31/28; G11C11/401; G11C11/413
Domestic Patent References:
| JPH07307100A | 1995-11-21 | |||
| JPS61292300A | 1986-12-23 | |||
| JP2001210095A | 2001-08-03 | |||
| JPS57105897A | 1982-07-01 | |||
| JPS63211198A | 1988-09-02 | |||
| JPH04212799A | 1992-08-04 | |||
| JPH06318400A | 1994-11-15 | |||
| JPH0675749A | 1994-03-18 | |||
| JPH05312918A | 1993-11-26 | |||
| JPH04211160A | 1992-08-03 | |||
| JPS61261895A | 1986-11-19 | |||
| JPH07211099A | 1995-08-11 |
Attorney, Agent or Firm:
Masaki Yamakawa