メモリ・セル構造、メモリ・セル・システム、およびメモリ・セル構造を製造するための方法

Title:

メモリ・セル構造、メモリ・セル・システム、およびメモリ・セル構造を製造するための方法

Document Type and Number:

Japanese Patent JP6865819

Kind Code:

B2

Abstract:

A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, and the first set depending on the second set.

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Inventors:

Takeo Yasuda
Koji Hosokawa
Masatoshi Ishii

Application Number:

JP2019521693A

Publication Date:

April 28, 2021

Filing Date:

October 25, 2017

Export Citation:

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Assignee:

Samsung Electronics Company Limited

International Classes:

G11C11/54; G06G7/60; G06N3/063

Domestic Patent References:

JP3250244A
JP4177699A

Foreign References:

US20120133538

Attorney, Agent or Firm:

Tadashige Ito
Tadahiko Ito
Shinsuke Onuki

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