PURPOSE: To improve the efficiency and precision of program debugging by recording specification information for setting a data write inhibition address and a write inhibition signal obtained by collating said specification information with an input from an address bus in hysteresis data bits of a main storage.

CONSTITUTION: Address information from an address bus 1 is inputted to an RAM2 and a main storage circuit 9. The RAM2 outputs a stored write inhibition signal 3 when information on a data write inhibition address to be specified coincides with information from the bus 1. The signal 3 is supplied to an AND gate 4 and an AND gate 6 after inversion 7. When a memory write signal 5 is supplied, the gate 4 generates an output 1 to record hysteresis information on access to the specified program address in a hysteresis data bit 9, and no data is written in a program area 90 by inhibiting access because the output of the gate 6 is 0. When the signal from the bus 1 does not coincide with said information to be specified, the signal 3 is 0 and data is rewritten in the address of the area 90 normally.