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Title:
MEMORY CONTROL METHOD AND DIGITAL RECORDING/ REPRODUCING DEVICE USING IT
Document Type and Number:
Japanese Patent JPH11164253
Kind Code:
A
Abstract:

To improve the application degree of main storage memory by provid ing shuffle memory that consists of plural memory banks, allocating a memory area for smoothing to a residual area of the shuffle memory and alternately making one bank input and output an external code word and to store it again and the other bank outputs an internal code word.

An interface part 50 is provided with a time stamp generating and controlling part 51, a 1st first-in first-out (FIFO) 52 and a 2nd FIFO 53. While the FIFO 52 writes data, the FIFO 53 reads stored data. By doing this write and read alternately, it is possible to prevent inter-input/output data collision. Memory for a smoothing/desmoothing buffer is allocated to a residual area of shuffled memory and utilized. A system is operated by a serial clock to share the memory.


Inventors:
ZE HYON RI
Application Number:
JP24333098A
Publication Date:
June 18, 1999
Filing Date:
August 28, 1998
Export Citation:
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Assignee:
LG ELECTRONICS INC
International Classes:
G11B20/10; G11B20/18; G11C7/10; G06F3/06; H04N5/92; H04N9/804; G11B5/008; H04N5/775; (IPC1-7): H04N5/92; G06F3/06; G11B20/18
Attorney, Agent or Firm:
Masaki Yamakawa