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Patent Searching and Data


Title:
MEMORY CONTROL SYSTEM FOR COMPUTER
Document Type and Number:
Japanese Patent JPH04290114
Kind Code:
A
Abstract:

PURPOSE: To increase the program execution speed by decreasing the frequency of access to an auxiliary storage device under memory control which performs paging.

CONSTITUTION: A main storage device as a real storage device and the auxiliary storage device as an external storage device are used and an execution type program which is divided into blocks of size corresponding to memory allocation units of the main storage device is paged in the block units between said main storage device and auxiliary storage device. In this memory control system for the computer, information regarding the frequencies of the use of the respective blocks is gathered by executing said program. When said program is started after the information gathering, blocks which are high in the use frequency are allocated preferentially to the main storage device according to the information regarding the use frequencies of the respective blocks and blocks which are low in use frequency are allocated to the auxiliary storage device from the beginning.


Inventors:
NAKADA GOJI
TARUMI HIROFUMI
TANABE SHIGEMI
KINOSHITA HISAKO
Application Number:
JP5486991A
Publication Date:
October 14, 1992
Filing Date:
March 19, 1991
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F3/06; (IPC1-7): G06F3/06
Attorney, Agent or Firm:
Shigenori Wada