To provide a system for configuring a memory controller that communicates with a memory device.

The memory controller includes a first set of pins composed of plural pins, in which each pin is associated with a data bit or an address bit, or both. The system includes a programmable logic block that is connected to the first set of pins of the memory controller, for using a second set of pins that is a subset of the first set of pins to enable data transfer between the memory device and the memory controller in accordance with the size of the memory device, such that the pins outside the second set of pins are available for one or more other applications.