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Patent Searching and Data


Title:
MEMORY CONTROLLING METHOD IN MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS5975350
Kind Code:
A
Abstract:

PURPOSE: To constitute so that each processor can utilize in common an assigned memory space, by writing a memory mapping table in an address converting device, by a master processor.

CONSTITUTION: A master processor 3 inputs in advance a memory mapping table output S0 for assigning slave memory spaces M1, M2WMn to a common memory space 4 of large memory size which the master processor 3 can control, to an address converting device 5. Subsequently, the memory spaces M1, M2W Mn are assigned to a prescribed position of the common memory space 4, as they are or dividing them. This common memory space 4 can be utilized by executing access by a data address signal SA and SB, respectively, by the master processor 3 and slave processors S1, S2WSn.


Inventors:
WASHINO MASATSUGU
NAKAJIMA MASATOSHI
NISHIO MASAHIRO
Application Number:
JP18599882A
Publication Date:
April 28, 1984
Filing Date:
October 25, 1982
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
G06F12/00; G06F12/02; G06F15/16; G06F15/167; G06F15/177; (IPC1-7): G06F13/00; G06F15/16
Attorney, Agent or Firm:
Shiro Mitsuishi