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Title:
MEMORY CORRECTION SYSTEM
Document Type and Number:
Japanese Patent JPS5634199
Kind Code:
A
Abstract:

PURPOSE: To make easy the correction of content of ROM, by providing the patching unit.

CONSTITUTION: The address information of the main memory unit 5 is stored in the address register 1, the patch detection circuit 3 in the patching unit a receives the address information via the bus 101, and the patch information storage circuit 2 detects the presence of patch with the comparison with the patch address preset. If patch is present, the significance signal 301 is fed to the address conversion circuit 4, the circuit 4 obtains the address of PROM area of the unit 5 corresponding to the patch address and feeds it to the unit 5. Thus, the unit 5 fetches the program information corresponded from ROM or PROM and feeds it to the data register 6.


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Inventors:
INOUE SUSUMU
OOSAWA JIROU
MAEKAWA MASAKADO
IKEDA ISAO
Application Number:
JP10895779A
Publication Date:
April 06, 1981
Filing Date:
August 27, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C17/00; G06F9/06; G11C29/00; G11C29/04; (IPC1-7): G11C17/00; G11C29/00



 
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