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Title:
MEMORY DEVICE FOR MULTI-PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPH02259866
Kind Code:
A
Abstract:

PURPOSE: To improve system efficiency by providing processors with related random access memories respectively so that data held in the memory cell of the memory of one side can be transferred simultaneously to the corresponding memory cell of another memory in response to a transfer control signal.

CONSTITUTION: An I/O means consisting of a first and a second RAMs 204, 208 including respectively plural independent but corresponding memory cells, buffers 232, 236 to give independent accesses to digital data stored respectively in the RAMs 204, 208 in response to an I/O signal, sensing amplifiers 234, 238, and an I/O multiplexer 230 is provided. Besides, a transfer control block 260 and a transfer logic block 270 for copying the digital data in the memory cell of one RAM simultaneously to the corresponding memory cell of another RAM in response to the transfer control signal are provided. Thus, the data can be transferred quickly between the memories related respectively to the processors in a system.


Inventors:
RENAADO JIYON YUUMINA
ROBAATO ANTONII ANSERUMO
Application Number:
JP16973389A
Publication Date:
October 22, 1990
Filing Date:
June 30, 1989
Export Citation:
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Assignee:
DIGITAL EQUIPMENT CORP
International Classes:
G06F12/00; G06F13/38; G06F15/16; G06F15/177; G11C11/00; G06F12/08; G11C11/413; (IPC1-7): G06F12/00; G06F12/08; G06F13/38; G06F15/16
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)