Title:
メモリデバイス
Document Type and Number:
Japanese Patent JP6595357
Kind Code:
B2
Abstract:
A memory device includes a semiconductor pillar, a first memory cell that includes a first memory film between a first word line and a side surface of the semiconductor pillar, a second memory cell that includes a second memory film between a second word line and the side surface of the semiconductor pillar, and a control circuit configured to carry out first and second operations on the first memory cell and the second memory cell during a reading operation. During the first operation, a read voltage is applied to the first word line and a read pass voltage is applied to the second word line, and during the second operation following the first operation, a first voltage is applied to the second word line, such that a potential of the second word line is lower than a potential of the semiconductor pillar.
Inventors:
Toshifumi Hashimoto
Application Number:
JP2016017377A
Publication Date:
October 23, 2019
Filing Date:
February 01, 2016
Export Citation:
Assignee:
Toshiba Memory Corporation
International Classes:
G11C16/34; G11C16/04; G11C16/08; G11C16/26
Domestic Patent References:
| JP2013004123A | ||||
| JP2013254537A | ||||
| JP7320487A | ||||
| JP2011096340A | ||||
| JP2011014817A | ||||
| JP2009266356A | ||||
| JP2007035214A | ||||
| JP2001325793A | ||||
| JP2002150789A |
Foreign References:
| US20120320678 |
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken