Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6421651
Kind Code:
A
Abstract:
PURPOSE: To reduce the number of memories in use by using a parity RAM enabling to read/write of plural bits at the same time as a memory for adding parity bit.
CONSTITUTION: As the parity bit added to data for data RAMs 20W27, the parity bits for 8 sets of RAMs of 32k×8-bit through an interface circuit 5 for 8-bit each into a parity RAM 4 comprising 32k×8-bit RAMs. Then the 8-bit parity bits stored is added to a data read one by one bit each corresponding to the data address by the operation of the circuit 5 at parity check and sent to a comparator circuit 7 to apply parity check. If any error is detected, a signal is sent.
Inventors:
KURAKAKE MITSUO
KINOSHITA JIRO
KAWAMURA FUMIO
KINOSHITA JIRO
KAWAMURA FUMIO
Application Number:
JP17842787A
Publication Date:
January 25, 1989
Filing Date:
July 17, 1987
Export Citation:
Assignee:
FANUC LTD
International Classes:
G06F12/16; G06F11/10; (IPC1-7): G06F12/16
Domestic Patent References:
| JPS57117198A | 1982-07-21 | |||
| JPS61214040A | 1986-09-22 |
Attorney, Agent or Firm:
Minoru Tsuji