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Patent Searching and Data


Title:
MEMORY DUMP DEVICE
Document Type and Number:
Japanese Patent JPH04182748
Kind Code:
A
Abstract:

PURPOSE: To perform rapid dumping by providing a mechanism freely attachable and detachable to and from the bus of the central processing unit and dumping the content of the main storage device to no-volatile memory.

CONSTITUTION: A reading control circuit 6 starts to operate when a reading command signal 202 is set from a central processing unit 2. At this time, the address counter within the reading control circuit is set to zero and the memory size is set to the length counter. The reading control circuit 6 sets an address counter to an address bus 101, sets a signal line 204, reads data from a main storage device 1, sets a signal line 203 and writes data on a non-volatile memory 4. These operations are repeated till the length counter becomes zero. Thus, with increasing a capacity of the main storage device, the stoppage of the computer system to take memory dump for a long time becomes unnecessary.


Inventors:
KOJIMA HAJIME
Application Number:
JP31183490A
Publication Date:
June 30, 1992
Filing Date:
November 16, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
G06F11/34; (IPC1-7): G06F11/34
Attorney, Agent or Firm:
Uchihara Shin