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Patent Searching and Data


Title:
MEMORY INTERLEAVE CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH04139549
Kind Code:
A
Abstract:

PURPOSE: To improve the bus sizing effect by providing the address comparators accordant with various bus sizes of a CPU.

CONSTITUTION: An address comparator 11 can set the highest access speed not only to the largest bus size but to other smaller bus sizes. That is, a hit state is secured even in such a state where the precedent and present accesses are equal to a byte access (8-bit access) together with a byte access different from the precedent access (difference between high and low bytes). In other words, a hit state is secured as long as the signal of an address bit AOO is different from the precedent access. Thus it is possible to prevent the deterioration of efficiency caused by various bus sizes of a CPU by providing the circuit 11 that can secure the coincidence among those bus sizes of the CPU. Then the deterioration of the memory access speed of the CPU can also be prevented.


Inventors:
HAMAGUCHI MOTOHIKO
NAKADA YOSHIHIRO
Application Number:
JP26439390A
Publication Date:
May 13, 1992
Filing Date:
October 01, 1990
Export Citation:
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Assignee:
NEC CORP
NEC SHIZUOKA LTD
International Classes:
G06F12/06; (IPC1-7): G06F12/06
Attorney, Agent or Firm:
Uchihara Shin