Title:
MEMORY MANAGEMENT UNIT
Document Type and Number:
Japanese Patent JPH01173143
Kind Code:
A
Abstract:
PURPOSE:To extend the physical address space of a computer system and at the same time to reduce the load of a processor due to the extension of a physical address by giving an access to an extension memory address space based on the extension address signal received from a selector. CONSTITUTION:A memory management unit 2 always monitors the signal delivered to a data bus DB and the control signal CS for peripheral control of an MPU 1 via an instruction decoder 6. Then an auxiliary address signal extended synchronously with the timing where the signal corresponding to an address bus AB is delivered in case an instruction that extends the address signal is carried out when the instruction of the MPU 1 is decoded. Thus the available physical address space of the MPU 1 can be extended by the unit 2. Furthermore no load is applied to the unit 2 at all except the minimum necessary initialization.
Inventors:
NOGUCHI TOMOAKI
MITANI SATORU
TOKITA TATSU
MITANI SATORU
TOKITA TATSU
Application Number:
JP33181987A
Publication Date:
July 07, 1989
Filing Date:
December 26, 1987
Export Citation:
Assignee:
TOSHIBA CORP
TOSHIBA MICRO CUMPUTER ENG
TOSHIBA MICRO CUMPUTER ENG
International Classes:
G06F12/06; G06F9/34; G06F12/02; (IPC1-7): G06F9/36; G06F12/06
Domestic Patent References:
| JPS59183449A | 1984-10-18 | |||
| JPS58115564A | 1983-07-09 |
Attorney, Agent or Firm:
Kazuo Sato (2 outside)