Title:
プログラム可能な最適化を有するメモリネットワークプロセッサ
Document Type and Number:
Japanese Patent JP7210078
Kind Code:
B2
Abstract:
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.
Inventors:
Dore, Michael Bee
Dobbs, Karl S
Solka, Michael Bee
Trosino, Michael Earl
Faulkner, Kenneth Earl
Bindros, Keith M
Aya, Samir
Bearsley, John Mark
Gibson, David A
Dobbs, Karl S
Solka, Michael Bee
Trosino, Michael Earl
Faulkner, Kenneth Earl
Bindros, Keith M
Aya, Samir
Bearsley, John Mark
Gibson, David A
Application Number:
JP2019100154A
Publication Date:
January 23, 2023
Filing Date:
May 29, 2019
Export Citation:
Assignee:
Coherent Logics Incorporated
International Classes:
G06F9/30; G06F9/34; G06F9/38
Domestic Patent References:
| JP200815589A |
Foreign References:
| US20100321579 |
Attorney, Agent or Firm:
Shigeki Yamakawa