Title:
MEMORY PROTECTING SYSTEM
Document Type and Number:
Japanese Patent JPS6228854
Kind Code:
A
Abstract:
PURPOSE: To protect a memory and to obtain security by generating interruption when a common address space is to be accessed erroneously.
CONSTITUTION: When a micro-CPU 1 is to access an address space common to all banks, an AND gate 101 is opened, an interruption request signal MCIR is generated to an interruption controller 12 and the controller 12 outputs an interruption request INT-REQ to the micro-CPU 1. At that time, the micro-CPU 1 generates an FF reset signal dollar mark B in an acknowledge cycle to rest the FF 104. Consequently, an interruption processing routine programmed in the common address space can be normally executed and access check can be available.
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Inventors:
SHIMOMURA TSUTOMU
Application Number:
JP16891785A
Publication Date:
February 06, 1987
Filing Date:
July 31, 1985
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F12/14; (IPC1-7): G06F12/14
Attorney, Agent or Firm:
Takehiko Suzue