Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP2022041503
Kind Code:
A
Abstract:
To provide a memory system that achieves improved reliability.SOLUTION: According to the embodiment, a memory system includes a semiconductor storage device 100 and a memory controller 200 that controls a read operation in the semiconductor storage device. The semiconductor storage device includes first and second memory cells MC0 stacked on a substrate, a word line WL0 connected to the first and second memory cells, a first bit line BL0 connected to the first memory cell, and a second bit line BL1 connected to the second memory cell. The read operation of a first state ("A") includes first and second read operations for reading data from the first and second memory cells, respectively. A first read voltage VA0 is applied to the word line during a first period in which the first read operation is performed, and a second read voltage VA1 is applied to the word line during a second period in which the second read operation is performed.SELECTED DRAWING: Figure 14
Inventors:
YAMADA HIDEKI
SHIRAKAWA MASANOBU
SHIRAKAWA MASANOBU
Application Number:
JP2020146732A
Publication Date:
March 11, 2022
Filing Date:
September 01, 2020
Export Citation:
Assignee:
KIOXIA CORP
International Classes:
G11C11/56; G11C16/04
Attorney, Agent or Firm:
Masatoshi Kurata
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Sanae Kaneko
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Sanae Kaneko