Title:
ターボデコーダ用メモリ
Document Type and Number:
Japanese Patent JP2005526443
Kind Code:
A
Abstract:
The decoding circuit comprises two decodes of type SISO (Soft-Input Soft-Output), a first decoder (14) and a second decoder (16), where each decoder can compute output extrinsic data on the basis of input extrinsic data issued by the other decoder, a memory store (31) for storing the extrinsic data, an interleaver (15) and a deinterleaver, that is an inverse interleaver (18). Output extrinsic data computed by a decoder are stored at an address of the output extrinsic data. The first decoder (14) reads the extrinsic data in a first order from the memory store (31), and the second decoder (16) reads the extrinsic data in a second order from the same memory store (31). The decoding is carried out by the decoding circuit (claimed) in an iterative manner, and the input data include a data vector (S1) and two parity vectors (P1,P2). The first order is a linear order, and the second orders is an interleaved order. The memory store comprises a read port and a write port. The memory store (31) is controlled by a clock of frequency two times higher than the frequency of the clock controlling the decoders (14,16), and also the decoder (20). In the third embodiment, the decoding circuit comprises a register for temporary storage of a component of a vector of input extrinsic data during the clock cycle controlling the decoders. The two decoders can be implemented by one decoder (20) also of type SISO, which functions alternatively according to a first mode corresponding to the functioning of the first decoder (14), and according to a second mode corresponding to the functioning of the second decoder (16). The decoding method (claimed) comprises a first step wherein the first decoder (14) reads in the linear manner the input extrinsic data stored in the memory (31), computes the output extrinsic data and writes each output extrinsic data at the address containing the corresponding input extrinsic data; and a second step wherein the second decoder (16) reads in the interleaved manner the input extrinsic data stored in the memory (31) and corresponding to the output extrinsic data computed by the first decoder (14) at the first step, computes the output extrinsic data and writes each output extrinsic data at the address containing the corresponding input extrinsic data. An electronic device (claimed) comprises the decoding circuit. A communication network (claimed) comprises at least one transmitter which can send coded signals, a transmission channel, a receiver which can receive the signals, and the decoding circuit. A program (claimed) comprises instructions of program code for executing the steps of the method when the program is executed on a processor.
Inventors:
Patrick, Bardonaire
Sebastian, Shappentier
Sebastian, Shappentier
Application Number:
JP2004506189A
Publication Date:
September 02, 2005
Filing Date:
May 07, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H03M13/27; H03M13/29; H04L1/00; (IPC1-7): H03M13/29; H03M13/27; H04L1/00
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Takeshi Sekine
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Takeshi Sekine