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Title:
MEMORY UNIT
Document Type and Number:
Japanese Patent JPS5577097
Kind Code:
A
Abstract:

PURPOSE: To make error corrections without increasing memory access time, by providing an auxiliary memory stored with ECC, in addition to a main memory.

CONSTITUTION: Data read out from main memory 22 at address 23 are checked by parity check circuit 25 and when no error is found, they are transferred, as they are, through cgange-over circuit 12. If an error is detected, access to auxiliary memory 27 stored with ECC generated by ECC generating circuit 26 is attained and read ECC is set to data register 28. Next, error data held in data register 24 and read ECC in data register 28 are inputted to error correction circuit 11 for error corrections and its output is transferred through change-over circuit 12. In this way, error corrections can be made without increasing the access time of the memory unit.


Inventors:
NAGAI MITSUHARU
Application Number:
JP14787978A
Publication Date:
June 10, 1980
Filing Date:
December 01, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F12/16; G11C29/00; (IPC1-7): G11C29/00



 
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