Title:
MEMORY WRITING CIRCUIT
Document Type and Number:
Japanese Patent JPH01128095
Kind Code:
A
Abstract:
PURPOSE: To make data processing by software simple and efficiently perform trinomial logical operation. CONSTITUTION: Two-word data of pattern figure data are read out of a memory 13 to a latch 5 and a latch 3, and selected and extracted by a shift circuit 7 and supplied to a trinomial logical operation circuit 11, source bit map data are similarly read to a latch 6 and a latch 4, and selected and extracted by a shift circuit 8 and supplied to the trinomial logical operation circuit 11, and destination bit map data read out of the memory 13 are read to a latch 10 and supplied to the trinomial logic operation circuit 11. Consequently, the respective figure data can be positioned, bit by bit, automatically by the latches and shift circuits of two-state constitution, and the need for software processing by an external processor is eliminated, so the trinomial logical operation processing can easily and efficiently be performed.
Inventors:
KUBOTA KAZUMI
KOBIYAMA TOMOHISA
OTE ICHIRO
ENOMOTO HIROMICHI
KOBIYAMA TOMOHISA
OTE ICHIRO
ENOMOTO HIROMICHI
Application Number:
JP28673987A
Publication Date:
May 19, 1989
Filing Date:
November 13, 1987
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G09G5/00; G09G1/00; G09G1/02; G09G5/32; G09G5/36; G09G5/39; (IPC1-7): G09G1/00; G09G1/02
Domestic Patent References:
| JPS60172085A | 1985-09-05 | |||
| JPS60136793A | 1985-07-20 |
Attorney, Agent or Firm:
Kazuko Tomita