PURPOSE: To improve a freedom degree by selecting the output of a memory arbitrary selecting circuit by means of the control of a CPU, and arbitrarily selecting a memory.

CONSTITUTION: Memories 51 to 54, an address decoder 3 to decode their addresses, a memory arbitrary selecting circuit 2 to select the arbitrary memory, OR circuits 41 to 44 to obtains the logical sum of the outputs of the address decoder 3 and the memory arbitrary selecting circuit 2, a CPU 1 to control the memories 51 to 54 and the memory arbitrary selecting circuit 2, and a control program memory 5 where the program executed by the CPU 1 is stored constitute the title memory. That is, it is composed so that the conventional memory simultaneous selecting circuit may be replaced with the memory arbitrary selecting circuit 2, and the memory may be arbitrarily selected by the control of the CPU 1. Thus, the using freedom degree can be improved.