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Title:
MEMORY
Document Type and Number:
Japanese Patent JPH04162297
Kind Code:
A
Abstract:

PURPOSE: To alleviate a load of a CPU and to improve a processing speed of an entire system by setting a code, sending a write signal, and then sequentially reading to output data for necessary code only by inputting a read signal.

CONSTITUTION: An address converter 1 converts a code indicating predetermined data to data corresponding to the address of a main memory 3 for storing the data to output it. A timing generator 4 outputs various types of control signals, outputs a preset pulse 106 to be generated in synchronization with a write signal 104 to be externally input and a countup clock 107 to be generated in synchronization with a read signal 105 to be input externally to an address counter 2, outputs a preset pulse 109 and a countdown clock 110 to a loop counter 5, and outputs a latch signal 112 to a latch circuit 6. Thus, the load of a CPU is alleviated, and a processing speed of an entire system is improved.


Inventors:
MARUYAMA TOSHIHIRO
Application Number:
JP28882790A
Publication Date:
June 05, 1992
Filing Date:
October 25, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C17/00; G11C11/413; (IPC1-7): G11C11/413; G11C17/00
Attorney, Agent or Firm:
Uchihara Shin



 
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