METHOD AND APPARATUS FOR HIGH-SPEED TRANSFER SLAVE REQUEST IN PACKET SWITCHING COMUTER SYSTEM

Japanese Patent JPH09172460

A

PROBLEM TO BE SOLVED: To obtain a system improving the processing efficiency of a processor request by providing a processor, a memory, a slave device and a controller. SOLUTION: A module 20 is combined with a system mutual connection controller 70 by a UPA port 60, and the controller 70 is combined with one or plural slave interfaces 80. The system controller 70 and the UPA interface 60 are mounted to a main processor chip and the interface 80 is mounted on a mother board but many other modes are possible. A module 25 includes a data path and cross path 90 which is combined with the controller 70 and the port 60. The UPA port 60 can be constituted as a part of the module 20 or 25. Through the use of a data path mechanism 90, reading data and writing data are transmitted.

JPH11120120	INTERFACE CIRCUIT FOR CARD BUS AND PC CARD FOR CARD BUS HAVING IT
WO/2018/103113	FPGA-BASED SYSTEM FOR CONVERTING LOCAL BUS INTO USB, AND CHIP
WO/2006/028663	SIDE-BY-SIDE INVERTED MEMORY ADDRESS AND COMMAND BUSES

UIRIAMU SHII BUAN RUU

JP19417396A

June 30, 1997

July 05, 1996

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SUN MICROSYSTEMS INC

G06F13/40; G06F15/163; G06F15/16; G06F15/177; (IPC1-7): H04L12/56; G06F15/163

Masaki Yamakawa

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