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Title:
METHOD AND APPARATUS FOR POLISHING
Document Type and Number:
Japanese Patent JP3916375
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To remove a Cu layer formed on a substrate, e.g. a semiconductor wafer, uniformly and to polish fine trenches made in the surface of the substrate and/or a Cu interconnection part formed in fine holes flatly and uniformly without causing any overpolish, e.g. dishing or erosion.
SOLUTION: The polishing method comprises a first polishing step for polishing a semiconductor wafer 20, having a Cu layer 31 formed in the interconnection trenches 30a, 30b made in the semiconductor wafer 20 and on the surface where the interconnection trenches are not made, until the Cu layer 31 has a specified film thickness by sliding the semiconductor wafer 20 on the polishing face on a turnable 9, and a second polishing step for removing the Cu layer 31 formed on the surface of the semiconductor wafer 20, along with a barrier metal layer 32, while leaving the Cu layer 31 formed in the interconnection trenches 30a, 30b sliding the semiconductor wafer 20 on the polishing face on the turntable 9 following to the first polishing step.


Inventors:
Norio Kimura
Tatsuya Obama
Application Number:
JP2000166682A
Publication Date:
May 16, 2007
Filing Date:
June 02, 2000
Export Citation:
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Assignee:
Ebara Corporation
International Classes:
H01L21/304; B24B37/00; B24B37/013; B24B37/07; B24B49/12; H01L21/02; H01L21/321; H01L21/768; (IPC1-7): H01L21/304; B24B37/00; B24B37/04; B24B49/12
Domestic Patent References:
JP8285514A
JP7235520A
JP2000012543A
JP2001053038A
JP2003517720A
Attorney, Agent or Firm:
Isamu Watanabe
Shintaro Hotta