Title:
深層学習人工ニューラルネットワークにおけるアナログニューラルメモリをプログラミングするための方法及び装置
Document Type and Number:
Japanese Patent JP7493065
Kind Code:
B2
Abstract:
A circuit for comparing current drawn by a selected memory cell (2908) for a vector-matrix-multiplier with a reference current corresponding to a current drawn by a reference matrix (2906), the circuit comprising: a first node; a first switch (2903); a second switch (2904); a transistor (2901) for comparing the current drawn by the selected memory cell and received from a the first node with a the reference current, wherein the circuit is configured such that :-in a first time period, the first node is coupled to the reference matrix (2906) by the first switch in order for the transistor to hold the reference current and-in a second time period, following the first time period, the first node is coupled to the selected memory cell in order for the transistor to compare the held reference current with the current drawn by the selected memory cell.
Inventors:
Tran, Huban
Tiwari, bipin
Doe, Nan
Latency, mark
Tiwari, bipin
Doe, Nan
Latency, mark
Application Number:
JP2023008471A
Publication Date:
May 30, 2024
Filing Date:
January 24, 2023
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
G11C11/56; G11C7/06; G11C16/26
Domestic Patent References:
| JP62140298A | ||||
| JP2008293619A | ||||
| JP2016513330A | ||||
| JP2000353393A | ||||
| JP8297983A |
Foreign References:
| WO2017200883A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation Wisdom International Patent and Trademark Office