Title:
METHOD AND APPARATUS FOR TESTING MULTI-PORTED MEMORY
Document Type and Number:
Japanese Patent JP3548126
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method and an apparatus for testing a multi-ported memory especially when one or a plurality of ports thereof are not directly accessible, without using any intermediate logic circuit.
SOLUTION: In this method and this system, multi-ported memory is separated into at least two parts used for testing one or a plurality of ports which is not directly accessible.
Inventors:
Dean Adams
Thomas J. Eken Road
Stephen El Gregore
Cam Ran Zalene
Thomas J. Eken Road
Stephen El Gregore
Cam Ran Zalene
Application Number:
JP2001048744A
Publication Date:
July 28, 2004
Filing Date:
February 23, 2001
Export Citation:
Assignee:
Cadence Design Systems, Inc.
International Classes:
G01R31/3183; G06F12/16; G11C29/52; G01R31/28; G11C29/56; (IPC1-7): G01R31/28; G06F12/16; G11C29/00
Domestic Patent References:
| JP63103984A |
Attorney, Agent or Firm:
Toshiyuki Ikeda
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