PURPOSE: To make the difference in delay time in bus lines having a fixed bit width negligible even when the layout of an integrated circuit is decided without paying attention to the balance in wiring capacity of the bus lines by cutting bus lines between macros having different sizes at every fixed length and automatically connecting bus buffers of the same number as that of the bus lines, and then, wiring the outputs of the bus buffers as bus lines between macros.

CONSTITUTION: Bus buffers are produced by inputting a limited wiring length, bus line names, and bus bit widths and bus wiring is started. Macros 11-15 are connected with each other through automatically produced bus lines 10. Lines A0-A3 which are bus lines between macros A and E discriminate whether or not the bus wiring length exceeds the limited wiring length and, when the length of a bus line exceeds the limited wiring length, disconnect the bus line and automatically connect the bit width of the bus lines to bus buffers 16 and 17. Bus lines A10-A13 which are the output lines of the bus buffer 16 receive interference from a macro C and the line A10 and A11-A13 are connected to the macro E through different wiring routes.