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Title:
METHOD FOR DESIGNATING PATH OF MULTINODE SCI COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPH10124472
Kind Code:
A
Abstract:

To constitute the same number of nodes in a linear array in a smaller configuration and to solve the problem of a waiting time in communication between the most separated node/processor by using a multi-dimensional node constitution, that is, processor constitution.

A multi-dimensional node, that is, a processor constitution is obtained. In this multi-dimensional constitution, that is, a multi-node multiple processor computer system 5, plural paths are provided among nodes 10. When one of the nodes 10 stops, the possibility of the remainder of this system is improved by allowing other paths which can be used for reaching the other nodes 10 in the system to be always present. When all the nodes 10 are functioning, communication between an origin node and a destination node in the node array is controlled by a first path designation rule group. When one node 10 is not functioning, a second rule group is replaced with the first rule group, or this is changed.


Inventors:
BRIAN D HOONANGU
BRIAN D MARIETTA
Application Number:
JP27827697A
Publication Date:
May 15, 1998
Filing Date:
September 25, 1997
Export Citation:
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Assignee:
HEWLETT PACKARD CO
International Classes:
G06F15/173; G06F11/00; G06F13/00; G06F15/16; G06F15/80; H04L12/42; H04L12/56; (IPC1-7): G06F15/16; H04L12/42; H04L12/56
Attorney, Agent or Firm:
Hideo Ueno