PURPOSE: To simply obtain information necessary in itself, as error information at the time when an arithmetic error interruption is generated, in the case a diffferent kind computer instruction is pseudo-executed.
CONSTITUTION: When a different kind computer instruction A is executed artificially, an interruption permitting/inhibiting flag CEI on a PSW 1 is retained by an arithmetic completion waiting/interruption inhibiting mechanism 5, and also, the CEI is turned off on the PSW 1, arithmetic completion in the course of execution is waited for, and thereafter, a source operand shown by an instruction A is copied to a specific register by a copying mechanism 6, a pseudo-execution mechanism 4 is actuated by a calling mechanism 7, and a pseudo-execution of the instruction A for following a pseudo-execution subroutine is executed. After the subroutine is executed, a result of operation returned through the specific register is copied to a distination operand shown by the instruction A by a copying mechanism 8, and when an arithmetic error interruption generating condition for following an architecture of a different kind computer is formed, an exclusive SVC is issued by an exclusive SVC(supervisor call) issuing mechanism 10, and an arithmetic error interruption is pseudo-generated.
TAKEUCHI YOICHIRO
MORI YOSHIYA
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