Title:
METHOD AND DEVICE FOR REDUCING CLOCK JITTER
Document Type and Number:
Japanese Patent JP3578135
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To automatically control jitter which is generated by the influence of waveform distortion or noise in ECL clock transmission, to a minimum.
SOLUTION: In a jitter control means 11, an input clock is distributed to (n) transmission lines (21-1 to 21-n) for transmitting the input clock with respective desired delay quantities, and the signal which is outputted together with a capacitive reflection pulse with which the clocks propagated through these (n) transmission lines are reflected on reception side terminals (CL1-CLn) and reflected again on transmitting side terminals (CS1-CSn) of (n) transmission lines and returned to the receiving side terminals, of any one reception side terminal selected by a select signal out of (n) reception side terminals is outputted as an output clock. The jitter control means composed of a frequency dividing circuit 12, phase comparing circuits 14 and 15, counters 15 and 17 and a variable delay circuit 13 updates the select signal until selecting a reception side terminal in which the capacitive reflection pulse is overlapped on the jitter portion of the input clock in the reception side terminal.
Inventors:
Naoki Kobayashi
Application Number:
JP2001347237A
Publication Date:
October 20, 2004
Filing Date:
November 13, 2001
Export Citation:
Assignee:
NEC
International Classes:
G06F1/12; H03K5/00; H04L7/00; H04L25/02; (IPC1-7): H04L7/00; H03K5/00; H04L25/02
Domestic Patent References:
| JP10135994A | ||||
| JP9008788A | ||||
| JP11205393A | ||||
| JP2001045071A | ||||
| JP7250104A | ||||
| JP2002501329A |
Attorney, Agent or Firm:
Masahiko Desk
Yasuhisa Tanizawa
Kawai Nobuaki
Yasuhisa Tanizawa
Kawai Nobuaki
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