PURPOSE: To simplify a circuit by ANDing memory contents and input information each time the information is inputted and delaying AND results, ORing all inputs by two pairs set for the respective inputs, and outputting the OR result of a determined pair unless two OR results match each other.
CONSTITUTION: The device is provided with memories 16a and 16b stored with coupling coefficients for respective inputs 15 separately in a excitative coupling group 14a and a suppressive coupling group 14b and AND gates 17a and 17b AND an input signal with a pulse train of coupling coefficients. The outputs of the AND gates 17a and 17b after being processed by a delay arithmetic circuit are ORed by OR gates 18a and 18b by the groups 14a and 14b. The OR result of the excitative group 14a and the OR result of the suppressive group 14b are combined by a gate circuit 19 and a circuit unit 20 calculates an output 21. When the OR results of both the OR gates 18a and 18b do not match each other, the output of the OR gate 18a is employed as the output value.
EGUCHI HIROTOSHI
KITAGUCHI TAKASHI
