PURPOSE: To attain programmable FIFO and its operation is not restrained by kinds of various operating conditions and processing by converting a 1st and 2nd binary signals into a first and a second gray code signals, and generating flag signals at the same time for both signals.

CONSTITUTION: A writing clock bus line 7 is connected with a gray code counter 15, which enumerates prescribed numbers. An asynchronous FIFO 12 consisting of RAM, generates a programmable state flag which represents that the number of words is N or fewer than full or empty. The value of N is a binary number. When a reset signal enters a line 9, outputs of the counters 15 and 19 are mutually compared with each other in a comparator and a logical circuit 28 in order that counters 15 and 19 generate state signals, full, half full, empty, and full-N or empty+N. In order to properly send the state signal to each system A and B, these state signals are outputted to each state line 17, 19. A FIFO with a state flag quick generation circuit which his programmable and is not restrained by kinds of operating conditions and processing is achieved.