Title:
METHOD AND DEVICE FOR TESTING ERROR IN MICROPROCESSOR
Document Type and Number:
Japanese Patent JP2004038954
Kind Code:
A
Abstract:
To provide a device that tests lockstep performance, and a corresponding method.
The device comprises two or more processors operable in a lockstep mode. The processors each have processor logic for executing a code sequence, a processor-specific resource referred to by the code sequence, a state machine for asserting a signal upon generation of a programmable event, and an output for supplying the asserted signal. The device further comprises a lockstep logic block operable to read and compare the respective outputs of the two or more processors. The processor outputs based on the code sequence execution are provided for the lockstep logic operable to read and compare the respective outputs of the two or more processors.
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Inventors:
SAFFORD KEVIN DAVID
PETSINGER JEREMY P
CARL P BURUMERU
PETSINGER JEREMY P
CARL P BURUMERU
Application Number:
JP2003161724A
Publication Date:
February 05, 2004
Filing Date:
June 06, 2003
Export Citation:
Assignee:
HEWLETT PACKARD DEVELOPMENT CO
International Classes:
G06F11/18; G06F11/00; G06F11/16; G06F11/22; G06F11/27; (IPC1-7): G06F11/18; G06F11/16; G06F11/22
Attorney, Agent or Firm:
Next student Okada
Naoya Fushimi
Yukari Hirano
Naoya Fushimi
Yukari Hirano
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