To improve the throughput of an entire system by transferring image data without completely occupying a bus.

An engine interface unit 15 incorporates a FIFO memory, for example, as an image buffer memory, the transfer state of image data is reported through this FIFO memory to a bus arbitrating circuit 16 and the bus arbitrating circuit 16 varies the priority concerning the bus use of a data transfer processing circuit provided in a device to become a bus master. When the almost full flag of the FIFO memory is established, the bus arbitrating circuit 16 prompts the stop of image data write into the FIFO memory by lowering the priority of image data transfer and when the almost empty flag is established, the bus arbitrating circuit 16 prompts the write of image data into the FIFO memory by raising the priority of image data transfer.